/*==================================================================
 * Copyright(c) Samsung Electronics Co., 1997,1998. All rights reseved.
 *
 * Verilog Behavioral Model of Synchronous DRAM 
 *
 * Device: -  16M SDRAM(2nd Gen., 3rd Gen., 4th Gen., 5th Gen.) 
 *	   -  64M SDRAM(2nd Gen., 3rd Gen., 4th Gen., 5th Gen.)
 *	   - 128M SDRAM(1st Gen., 2nd Gen.,)
 *	   - 256M SDRAM(2nd Gen.)
 *
 * Description : This is a synchrounous high data rate DRAM, 
 *		 fabricated with SAMSUNG's high performance  
 *               CMOS technology.                                
 *
 * Developer   : Jae-Ha Kim.
 *  		 CAE Team. Semiconductor R&D Centor. 
 *		 Semiconductor Division. Samsung Electronics Co.
 *
 *==================================================================*/
`timescale    1ns / 10ps
 
`define K1	1024
`define M1	1048576
`define BYTE	8
    
`ifdef M64
/////////////////////////////////////////////////////////////////////////////
	`ifdef S50 //M64
	    `define tCCmin  5.0			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    5			// clock minimun cycle time at cas latency=3
	    `define tCC3    5			// clock minimun cycle time at cas latency=3
	    `define tCH     2			// clock high pulse width
	    `define tCL     2			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     1			// input hold time
	    `define tRRD    10			// row to row delay(min)
	    `define tRCD    15			// ras to cas delay(min)
	    `define tRP     15			// row precharge time(min)	
	    `define tRASmin 40			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     55			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    5.0			// col. address to col. address delay:
	    `define tSAC4   4.5			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   4.5			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   4.5			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   4.5			// CLK to output in Hi-Z at cas latency=3	
	`endif //end of S50
	`ifdef S60 //M64
	    `define tCCmin  6.0			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC3    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC2    10.0		// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     1.0			// input hold time
	    `define tRRD    12			// row to row delay(min)
	    `define tRCD    18			// ras to cas delay(min)
	    `define tRP     18			// row precharge time(min)	
	    `define tRASmin 42			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     60			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    6.0			// col. address to col. address delay:
	    `define tSAC4   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S60
	`ifdef S75 //M64
	    `define tCCmin  7.5			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC3    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC2    10			// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     0.8			// input hold time
	    `define tRRD    15			// row to row delay(min)
	    `define tRCD    20			// ras to cas delay(min)
	    `define tRP     20			// row precharge time(min)	
	    `define tRASmin 45			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     65			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    7.5			// col. address to col. address delay:
	    `define tSAC4   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S75
`endif //end of M64

`ifdef M128
/////////////////////////////////////////////////////////////////////////////
	`ifdef S50 //M128
	    `define tCCmin  5.0			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    5			// clock minimun cycle time at cas latency=3
	    `define tCC3    5			// clock minimun cycle time at cas latency=3
	    `define tCH     2			// clock high pulse width
	    `define tCL     2			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     1			// input hold time
	    `define tRRD    10			// row to row delay(min)
	    `define tRCD    15			// ras to cas delay(min)
	    `define tRP     15			// row precharge time(min)	
	    `define tRASmin 40			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     55			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    5.0			// col. address to col. address delay:
	    `define tSAC4   4.5			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   4.5			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   4.5			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   4.5			// CLK to output in Hi-Z at cas latency=3
	`endif //end of S50
	`ifdef S60 //M128
	    `define tCCmin  6.0			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC3    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC2    10.0		// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     1.0			// input hold time
	    `define tRRD    12			// row to row delay(min)
	    `define tRCD    18			// ras to cas delay(min)
	    `define tRP     18			// row precharge time(min)	
	    `define tRASmin 42			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     60			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    6.0			// col. address to col. address delay:
	    `define tSAC4   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S60
	`ifdef S75 //M128
	    `define tCCmin  7.5			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC3    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC2    10			// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     0.8			// input hold time
	    `define tRRD    15			// row to row delay(min)
	    `define tRCD    20			// ras to cas delay(min)
	    `define tRP     20			// row precharge time(min)	
	    `define tRASmin 45			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     65			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    7.5			// col. address to col. address delay:
	    `define tSAC4   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S75
`endif //end of M128

`ifdef M256
/////////////////////////////////////////////////////////////////////////////
	`ifdef S50 //M256
	    `define tCCmin  5.0			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    5			// clock minimun cycle time at cas latency=3
	    `define tCC3    5			// clock minimun cycle time at cas latency=3
	    `define tCH     2			// clock high pulse width
	    `define tCL     2			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     1			// input hold time
	    `define tRRD    10			// row to row delay(min)
	    `define tRCD    15			// ras to cas delay(min)
	    `define tRP     15			// row precharge time(min)	
	    `define tRASmin 40			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     55			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    5.0			// col. address to col. address delay:
	    `define tSAC4   4.5			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   4.5			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   4.5			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   4.5			// CLK to output in Hi-Z at cas latency=3
	`endif //end of S50
	`ifdef S60 //M256
	    `define tCCmin  6.0			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC3    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC2    10.0		// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     1.0			// input hold time
	    `define tRRD    12			// row to row delay(min)
	    `define tRCD    18			// ras to cas delay(min)
	    `define tRP     18			// row precharge time(min)	
	    `define tRASmin 42			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     60			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    6.0			// col. address to col. address delay:
	    `define tSAC4   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S60
	`ifdef S75 //M256
	    `define tCCmin  7.5			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC3    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC2    10			// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     0.8			// input hold time
	    `define tRRD    15			// row to row delay(min)
	    `define tRCD    20			// ras to cas delay(min)
	    `define tRP     20			// row precharge time(min)	
	    `define tRASmin 45			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     65			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    7.5			// col. address to col. address delay:
	    `define tSAC4   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S75
`endif //end of M256

`ifdef M512
/////////////////////////////////////////////////////////////////////////////
	`ifdef S50 //M512
	    `define tCCmin  5.0			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    5			// clock minimun cycle time at cas latency=3
	    `define tCC3    5			// clock minimun cycle time at cas latency=3
	    `define tCH     2			// clock high pulse width
	    `define tCL     2			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     1			// input hold time
	    `define tRRD    10			// row to row delay(min)
	    `define tRCD    15			// ras to cas delay(min)
	    `define tRP     15			// row precharge time(min)	
	    `define tRASmin 40			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     55			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    5.0			// col. address to col. address delay:
	    `define tSAC4   4.5			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   4.5			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   4.5			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   4.5			// CLK to output in Hi-Z at cas latency=3
	`endif //end of S50
	`ifdef S60 //M512
	    `define tCCmin  6.0			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC3    6.0			// clock minimun cycle time at cas latency=3
	    `define tCC2    10.0		// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     1.0			// input hold time
	    `define tRRD    12			// row to row delay(min)
	    `define tRCD    18			// ras to cas delay(min)
	    `define tRP     18			// row precharge time(min)	
	    `define tRASmin 42			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     60			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    6.0			// col. address to col. address delay:
	    `define tSAC4   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.0			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.0			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S60
	`ifdef S75 //M512
	    `define tCCmin  7.5			// clock minimum cycle time
	    `define tCCmax  1000		// clock maximun cycle time
	    `define tCC4    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC3    7.5			// clock minimun cycle time at cas latency=3
	    `define tCC2    10			// clock minimun cycle time at cas latency=2
	    `define tCH     2.5			// clock high pulse width
	    `define tCL     2.5			// clock low pulse width	
	    `define tSS     1.5			// input setup time	
	    `define tSH     0.8			// input hold time
	    `define tRRD    15			// row to row delay(min)
	    `define tRCD    20			// ras to cas delay(min)
	    `define tRP     20			// row precharge time(min)	
	    `define tRASmin 45			// row active minimum time
	    `define tRASmax 100000		// row active maximum time
	    `define tRC     65			// row cycle time(min)	
            `define tRDL    2			// Last data in to row precharge : 2 clk
	    `define tCCD    7.5			// col. address to col. address delay:
	    `define tSAC4   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ4   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC3   5.4			// CLK to valid output delay at cas latency=3
	    `define tSHZ3   5.4			// CLK to output in Hi-Z at cas latency=3
	    `define tSAC2   6			// CLK to valid output delay at cas latency=2
	    `define tSHZ2   6			// CLK to output in Hi-Z at cas latency=2
	`endif //end of S75
`endif //end of M512


`ifdef DPD_PIN
module
sdram(clk, csb, cke, ba, ad, rasb, casb, web, dqm, dqi, dpdb);
`else
module
sdram(clk, csb, cke, ba, ad, rasb, casb, web, dqm, dqi);
`endif
    `ifdef M16
	`define TBITS	16*`M1
	`define nBank	2
        `define ADDRTOP	10
	`define	ADDR_AP	10
    `endif
    `ifdef M64
	`define TBITS		64*`M1
	`define	ADDR_AP	10
    	`ifdef NBANK2
      	    `define nBank	2	
	    `ifdef X32
	    	`define ADDRTOP	11
	    `else
            	`define ADDRTOP	12
	    `endif
    	`endif
        `ifdef NBANK4
     	    `define nBank	4	
	    `ifdef X32
            	`define ADDRTOP	10
	    `else
	    	`define ADDRTOP	11
	    `endif
    	`endif
    `endif
    `ifdef M128
	`define TBITS	128*`M1
	`define nBank	4
        `define ADDRTOP	11
	`define	ADDR_AP	10
    `endif
    `ifdef M256
	`define TBITS	256*`M1
	`define nBank	4
        `define ADDRTOP	12
	`define	ADDR_AP	10
    `endif
    `ifdef M512
	`define TBITS	512*`M1
	`define nBank	4
        `define ADDRTOP	12
	`define	ADDR_AP	10
    `endif

`ifdef M16
        `ifdef G2
                `define M16G2_M641G
	`else
                `define M16G3_M64G2
                `define M64G3_M128_M256
        `endif
`endif

`ifdef M64
                `define M64_M128_M256    // for prech_reg 
        `ifdef G1
                `define M16G2_M641G
        `else
        `ifdef G2
                `define M16G3_M64G2
        `else
                `define M16G4_M64G3
                `define M64G3_M128_M256
        `endif
        `endif
`endif

`ifdef M128  // 98.6.30 BYC
                `define M64_M128_M256    // for prech_reg 
		`define M128_M256        // RFU, c_addr 10->11 
                `define M64G3_M128_M256  // from M64G3
                `define M16G4_M64G3
`endif
`ifdef M256  // 98.6.30 BYC
                `define M64_M128_M256    // for prech_reg 
		`define M128_M256        // RFU, c_addr 10->11 
                `define M64G3_M128_M256  // from M64G3
                `define M16G4_M64G3
`endif
`ifdef M512  // 09.5.14 reum
                `define M64_M128_M256    // for prech_reg 
		`define M128_M256        // RFU, c_addr 10->11 
                `define M64G3_M128_M256  // from M64G3
                `define M16G4_M64G3
`endif

`ifdef tCC1
`else
	`define NO_CL1
`endif
`ifdef tSAC1
`else
	`define NO_CL1
`endif
`ifdef tSHZ1
`else
	`define NO_CL1
`endif
`ifdef tCC2
`else
	`define NO_CL2
`endif
`ifdef tSAC2
`else
	`define NO_CL2
`endif
`ifdef tSHZ2
`else
	`define NO_CL2
`endif
`ifdef tCC3
`else
	`define NO_CL3
`endif
`ifdef tSAC3
`else
	`define NO_CL3
`endif
`ifdef tSHZ3
`else
	`define NO_CL3
`endif

`ifdef M128_M256
    `ifdef X4
    	`define M128_M256_X4			// 98.6.30 BYC
    	`define B		4		// number of bit(x4)
    	`define nCOL		11
    	`define PAGEDEPTH	2048
        `define nDQM		1
    `endif
    `ifdef X8
        `define B		8		// number of bit(x8)
    	`define nCOL		10
    	`define PAGEDEPTH	1024
    	`define nDQM		1
    `endif
    `ifdef X16
    	`define B		16		// number of bit(x16)
    	`define nCOL		9
    	`define PAGEDEPTH	512
        `define nDQM		2
    `endif
    `ifdef X32
    	`define B		32		// number of bit(x32)
    	`define nCOL		8
    	`define PAGEDEPTH	256
        `define nDQM		4
    `endif
`else
    `ifdef X4
    	`define B		4		// number of bit(x4)
    	`define nCOL		10
    	`define PAGEDEPTH	1024
        `define nDQM		1
    `endif
    `ifdef X8
        `define B		8		// number of bit(x8)
    	`define nCOL		9
    	`define PAGEDEPTH	512
    	`define nDQM		1
    `endif
    `ifdef X16
    	`define B		16		// number of bit(x16)
    	`define nCOL		8
    	`define PAGEDEPTH	256
        `define nDQM		2
    `endif
    `ifdef X32
    	`define B		32		// number of bit(x32)
    	`define nCOL		8
    	`define PAGEDEPTH	128
        `define nDQM		4
    `endif
`endif

`ifdef	tRDL
`else
	`define	tRDL	1
`endif

`ifdef DPD_CMD
	`define DPD
`endif
`ifdef DPD_PIN
	`define DPD
`endif

  `define HB		`B/2
  `define BIT		`B-1:0
  `define BIT_C		`nCOL-1:0
  `define BIT_T		`nCOL+`ADDRTOP:0
  `define nWORD		`TBITS/`B/`nBank
  `define WORD		`nWORD-1:0
  
  inout   [`BIT]  dqi;
  input   [`nBank/2-1:0] ba;
  input   [`ADDRTOP:0]  ad;
  input   rasb,casb,web;
  input   clk,cke,csb;
  input   [`nDQM-1:0] dqm;
`ifdef DPD_PIN
  input   dpdb;
`endif
  
/*
  `ifdef M64
    	`include "m64.ac"
  `endif
  `ifdef M16
    	`include "m16.ac"
  `endif
  `ifdef M128
    	`include "m128.ac"
  `endif
  `ifdef M256
    	`include "m256.ac"
  `endif
*/

  parameter       pwrup_time = 200000, pwrup_check = 0;

`protected

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`endprotected
endmodule
